Shane O'Connell
LinkedIn |
GitHub |
Website
Toronto, Canada
Objective
My goal is to find employment income, as well as a group of like-minded people to work on engineering problems. I would prefer to work on a team that is trying to accomplish something that is considered technically difficult. I am open to working on many different types of engineering problems.
Work Experience
shane.oconnell.cc Principal Engineer
November 2022 - Present
- Experienced the events that led me to creating a page on my website about being trapped in my apartment
- Wrote a custom Linux package manager written in Python
- Wrote software for managing large amounts of information saved from the Internet
- Designed and implemented a custom network firewall, which uses a custom protocol over a serial cable in an attempt to prevent the Intel Management Engine from accessing the Internet using Ethernet
- Became interested in radio and drones
- Became interested in doing projects related to lab grown meat
- Did not make any employment income during this period
RapidSilicon Principal Engineer
February 2022 - November 2022
- Responsible for the development of RapidSilicon's timing analysis software
- Partially completed code to allow the VPR open source placement and routing engine to interface with OpenSTA to analyze timing, rather than using the Tatum timing analyzer that is part of VPR
Groq Compiler Engineer
January 2021 - February 2022
- Worked on an MLIR-based compiler written in C++ that compiles neural network models written in PyTorch and ONNX for the Groq TSP
- Performed optimizations which resulted in significant improvements in compile time as well as execution time on the Groq TSP
- Designed improvements to the representation of graphs between compiler passes which reduced the complexity of representing graphs and reduced the complexity of the algorithms that operate on it
Intel Deep Learning Software Engineer
April 2016 - January 2021
- One of three founding members on the Deep Learning Accelerator project for Intel FPGAs
- Designed hardware (RTL) for accelerating neural networks on FPGAs
- Played a strong technical role over the life of the project, by identifying new optimization opportunities and providing guidance to newer members of the team
- Implemented hardware designs using a combination of SystemVerilog and OpenCL C using the Intel FPGA SDK for OpenCL
- Provided feedback and suggestions for optimizations to improve the Intel FPGA OpenCL compiler based on real-world use
Altera Senior Software Engineer
May 2015 - March 2016
- Developed and maintained software code in C and C++ for the FPGA SDK for OpenCL
- Implemented new features, fixed bugs, and improved performance of the runtime and Linux device driver code
- After December 2015, this position was at Intel, which acquired Altera
Altera Senior Software Engineer
September 2013 - April 2015
- Worked on the TimeQuest timing analyzer, part of the Quartus FPGA design software
- Developed and maintained software code for a large C++ application that analyzes circuit timing using multi-threaded graph traversals on large graphs with millions of edges and nodes
- Analyzed performance with code analysis tools and implemented changes to improve performance
Avalon Microelectronics Senior Design Engineer
April 2008 - August 2013
- Designed RTL hardware cores in SystemVerilog for FPGAs to implement various networking protocols including OTN, Ethernet, and Fibre Channel
- Analyzed designs using the Quartus FPGA software to find ways to reduce area and improve performance
- Before starting as a regular employee in May 2010, worked at the company as a student for three four-month co-op work terms in April 2008, January 2009, and August 2009
- After December 2010, this position was at Altera, which acquired Avalon Microelectronics
Consilient Software Engineer
January 2007 - December 2007
- Developed new features and fixed bugs in the Windows Mobile version of Consilient's primary consumer software application, Consilient Push, using C# and C++
- Performed black box testing of the Java version of Consilient Push
- Worked at the company for two four-month student co-op work terms in January 2007 and August 2007
National Research Council Technical Support
April 2006 - August 2006
- Provided technical support for networking and computers issues
- Created a system for forwarding log messages from Linux, UNIX, and Windows machines to a central server
- This position was a four-month student co-op work term
kryptOS Founder
January 2002
- Became interested in operating systems and assembly language while in high school
- Created a website describing my plan to create an operating system which was able to compete with Microsoft Windows
- Published initial source code
- The project did not proceed very far, however it did reach the point where the operating system was able to boot and print a message
Animorph90's Animorphs / ani-morphs.com Founder
~1997
- Created a website which provided information for fans of the Animorphs book series
- Wrote JavaScript code to implement interactive browser-based quizzes and short stories which allowed arbitrary words to be replaced (mad libs)
- Experienced copyright infringement when I noticed that my JavaScript quiz code had been copied verbatim into another fan website which had a quiz
- Was sent an Animorphs card game for free by the company that made it in order for me to review it on my website, though if I remember correctly I believe I did not follow through and write the review
Skills
Programming Languages
C++, Python, SystemVerilog, OpenCL, HTML, JavaScript/TypeScript
Tools
git, bash, vim, tmux
Education
University of Toronto
- Master of Engineering, Computer Engineering (2018)
Memorial University of Newfoundland
- Bachelor of Engineering, Computer Engineering (2010)
Publications
- DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration 28th International Conference on Field Programmable Logic and Applications (FPL), August 2018 (with 10 other co-authors) https://doi.org/10.1109/FPL.2018.00077
- Harnessing Numerical Flexibility for Deep Learning on FPGAs HEART 2018: Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, June 2018 (with 10 other co-authors) https://doi.org/10.1145/3241793.3241794
- An OpenCL™ Deep Learning Accelerator on Arria 10 FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 2017 (with 4 other co-authors) https://doi.org/10.1145/3020078.3021738
Patents
- Floating-point decomposition circuitry with dynamic precision Patent pending, published 2020-07-09 (with 2 other co-inventors)
- Fast filtering US Patent 10083007, granted 2018-09-25 (with 3 other co-inventors)
- Methods and apparatus for rapid interrupt lookups US Patent 9811484, granted 2017-11-07 (with no other co-inventors)
Last Update: 2026-05-15